Differential Crosstalk Mitigation in the Pin Field Area of SerDes Channel with Trace Routing Guidance

Abstract

Crosstalk noise on the printed circuit board is usually decreased by adding shielding ground (GND). In the trace routing area, the shielding vias are added to isolate the coupling between different traces. In the ball gate array (BGA) and pin field area, assigning more GND pins has demonstrated the effectiveness of crosstalk reduction between signals. However, such design decreases the signal to ground (S:G) ratio dramatically, herein, it is not suitable for applications that require high signal pin density. Unlike the treatment in the conventional methodology, in this paper, the differential crosstalk is mitigated by using the principle of symmetry on two adjacent differential signal pairs in the BGA and pin field regions. New full pin map patterns are proposed and compared with the conventional full pin map patterns. Without sacrificing the S:G ratio, the proposed maps prove the superiority in mitigating both differential far-end and near-end integrated crosstalk noise. To maintain the low crosstalk level in the entire link path, guidance of differential trace routing is provided and demonstrated in the details. All models in this paper satisfy SerDes channel designing and manufacturing requirements.

Department(s)

Electrical and Computer Engineering

Comments

This work was supported by the National Science Foundation under Grant IIP-1440110.

Keywords and Phrases

Channel Operating Margin (COM); Crosstalk Mitigation; Differential Trace Routing; Integrated Crosstalk Noise (ICN); Integrated Crosstalk Ratio (ICR); Pin Map Patterns; SerDes

International Standard Serial Number (ISSN)

0018-9375

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2019 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2019

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