An Application of System Level Efficient ESD Design for High- Speed USB3.x Interface
Abstract
A high-speed USB3.x IO is analyzed using the System level efficient ESD design methodology [1] using on-board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation.
Recommended Citation
P. Wei et al., "An Application of System Level Efficient ESD Design for High- Speed USB3.x Interface," Proceedings of the 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (2018, Reno, NV), ESD Association, Sep 2018.
The definitive version is available at https://doi.org/10.23919/EOS/ESD.2018.8509765
Meeting Name
2018 40th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 (2018: Sep. 23-28, Reno, NV)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Design; Design Methodology; ESD protection devices; High Speed; Measurement and simulation; On-chip ESD protection; System levels; Electrostatic devices
International Standard Book Number (ISBN)
978-1-5853-7302-4
International Standard Serial Number (ISSN)
0739-5159
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2018 ESD Association, All rights reserved.
Publication Date
01 Sep 2018
