Analysis on Via Design for Impedance Mismatch Minimization in High Speed Channel

Author

Jaemin Lim
Joungho Kim
DongHyun Kim, Missouri University of Science and TechnologyFollow
For full list of authors, see publisher's website.

Recommended Citation

J. Lim et al., "Analysis on Via Design for Impedance Mismatch Minimization in High Speed Channel," Proceedings of the 7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition, APEMC 2016 (2016, Shenzhen, China), May 2016.

Meeting Name

7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition, APEMC 2016 (2016: May 18-21, Shenzhen, China)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Publication Date

01 May 2016