Masters Theses

Abstract

"This paper describes the organization and failure analysis of various types of binary address decoders. Logical type faults are considered and all possible faulty output patterns, resulting from these faults, are derived. A basic theory is developed, showing that these failure patterns are independent of the decoder size and organization. Digital simulation programs were used as an aid in the development of this theory. Results of the simulation are provided in the appendix"--Abstract, page ii.

Advisor(s)

Szygenda, Stephen A.

Committee Member(s)

Tracey, James H.
Ho, C. Y. (Chung You), 1933-1988

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Electrical Engineering

Publisher

University of Missouri--Rolla

Publication Date

1969

Pagination

vi, 118 pages

Note about bibliography

Includes bibliographical references (page 42).

Rights

© 1969 Kanaiyalal Jekisondas Gandhi, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Subject Headings

Failure time data analysisBinary system (Mathematics)Signal theory (Telecommunication)Coding theory

Thesis Number

T 2287

Print OCLC #

5154962

Electronic OCLC #

835633434

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