Masters Theses
Using a VHDL testbench for transistor-level simulation and power calculation of NULL convention asynchronous digital circuits
Abstract
"This thesis focuses on describing the method for simulating transistor-level design with a VHDL testbench and calculation of the average power per operation for NULL Convention Logic (NCL) asynchronous delay-insensitive digital circuits, using one of the industry standard "synchronous" design tool suites, Mentor Graphics"--Abstract, page iii.
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Publisher
University of Missouri--Rolla
Publication Date
Fall 2004
Pagination
viii, 73 pages
Note about bibliography
Includes bibliographical references.
Rights
© 2004 Anshul Singh, All rights reserved.
Document Type
Thesis - Citation
File Type
text
Language
English
Subject Headings
VHDL (Computer hardware description language)
Logic design
Logic, Symbolic and mathematical
Transistor circuits -- Simulation methods
Thesis Number
T 8688
Print OCLC #
62080451
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.
http://merlin.lib.umsystem.edu/record=b5371316~S5Recommended Citation
Singh, Anshul, "Using a VHDL testbench for transistor-level simulation and power calculation of NULL convention asynchronous digital circuits" (2004). Masters Theses. 3612.
https://scholarsmine.mst.edu/masters_theses/3612
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