“This thesis focuses on the implementation of a FPGA based processor for processing compressed binary images without decompressing them. The processor implements a systolic algorithm to find the difference between two binary images in Run Length Encoded (RLE) format. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed. The Xilinx PCI LogiCORE is used to interface the processor to the PCI bus. The use of a pre-optimized Intellectual Property core for the PCI bus interface reduces the design cycle time and allows the designer to concentrate on new features to be implemented in the design. The advantages and limitations of design using reusable intellectual property cores are also discussed”--Abstract, page iii.
Pottinger, Hardy J., 1944-
McCracken, Theodore E.
Electrical and Computer Engineering
M.S. in Electrical Engineering
University of Missouri--Rolla
ix, 63 pages
© 2000 Balakrishnan Venkatasamy Subbulakshmi, All rights reserved.
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Electronic access to the full-text of this document is restricted to Missouri S&T users. Otherwise, request this publication directly from Missouri S&T Library or contact your local library.http://merlin.lib.umsystem.edu/record=b4498585~S5
Venkatasamy Subbulakshmi, Balakrishnan, "Design and implementation of a FPGA based systolic processor for compressed images" (2000). Masters Theses. 1962.
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