Masters Theses
Abstract
“This thesis focuses on the implementation of a FPGA based processor for processing compressed binary images without decompressing them. The processor implements a systolic algorithm to find the difference between two binary images in Run Length Encoded (RLE) format. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed. The Xilinx PCI LogiCORE is used to interface the processor to the PCI bus. The use of a pre-optimized Intellectual Property core for the PCI bus interface reduces the design cycle time and allows the designer to concentrate on new features to be implemented in the design. The advantages and limitations of design using reusable intellectual property cores are also discussed”--Abstract, page iii.
Advisor(s)
Pottinger, Hardy J., 1944-
Committee Member(s)
McCracken, Theodore E.
Erçal, Fikret
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Publisher
University of Missouri--Rolla
Publication Date
Summer 2000
Pagination
ix, 63 pages
Note about bibliography
Includes bibliographical references (pages 61-62).
Rights
© 2000 Balakrishnan Venkatasamy Subbulakshmi, All rights reserved.
Document Type
Thesis - Restricted Access
File Type
text
Language
English
Thesis Number
T 7814
Print OCLC #
45694271
Recommended Citation
Venkatasamy Subbulakshmi, Balakrishnan, "Design and implementation of a FPGA based systolic processor for compressed images" (2000). Masters Theses. 1962.
https://scholarsmine.mst.edu/masters_theses/1962
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