Power bus design is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation formulation is presented herein to model arbitrary multilayer power bus structures including vertical discontinuities associated with surface mount (SMT) decoupling capacitor interconnects. Both conductor and dielectric losses are incorporated, and included into the first principles formulation. The agreement of modeling and measurements demonstrates its effectiveness and utilization in power bus designs.

Meeting Name

2nd Asia-Pacific Conference on Environmental Electromagnetics (2000: May 3-7, Shanghai, China)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

DC Power Bus Modeling; Arbitrary Multilayer Power Bus Structures; Circuit Extraction Approach; Conductor Losses; Conductors (Electric); Dielectric Losses; Digital Integrated Circuits; High-Speed Digital Circuit; High-Speed Digital Designs; High-Speed Integrated Circuits; Integral Equations; Integrated Circuit Design; Mixed-Potential Integral Equation Formulation; Surface Mount Decoupling Capacitor Interconnects; Surface Mount Technology; Vertical Discontinuities; Buses; Design; Dielectric Devices; Integrated Circuit Manufacture; Reconfigurable Hardware; Arbitrary Multilayers; Circuit Extraction; Decoupling Capacitor; High Speed Digital Design; Mixed Potential Integral Equations; Modeling And Measurement; Power-Bus Structure

International Standard Book Number (ISBN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2000 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2000