Implementation Of Photo-imagers In A 0.8 Μm Double-polysilicon Bipolar Process
Abstract
High-speed, low-power image processing can be performed by architectures incorporating on-chip, near-sensor processing in high-speed bipolar processes. To date, most imaging architectures have been implemented in CMOS or CCD processes. This paper discusses characteristics of 1-D imagers fabricated in a 0.8 μm double-polysilicon bipolar process for use in integrated remote imager applications with wireless links. The imager consists of continuous-time logarithmic photodetectors coupled to Darlington buffers.
Recommended Citation
M. D. Rowley et al., "Implementation Of Photo-imagers In A 0.8 Μm Double-polysilicon Bipolar Process," Proceedings of the IEEE Bipolar Bicmos Circuits and Technology Meeting, pp. 116 - 119, Institute of Electrical and Electronics Engineers, Dec 1997.
Department(s)
Electrical and Computer Engineering
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2025 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Dec 1997
