Abstract
A novel spike-based computation architecture has been developed which represents synaptic weights in time. An analog chip with 32 neurons, 1024 synapses and an AER block has been fabricated in 0.5μm technology. A digital implementation of the architecture having 6,144 neurons and 100,352 synapses on an FPGA is also described. A digital controller for routing spikes can processes up to 34 million synapses per second. The architecture is called the time machine as it operates on timing events and uses time to store weights. The time machine is general enough for implementing many spike-based algorithms yet provides flexibility and configurability. © 2011 IEEE.
Recommended Citation
V. Garg et al., "The Time Machine: A Novel Spike-based Computation Architecture," Proceedings IEEE International Symposium on Circuits and Systems, pp. 685 - 688, article no. 5937658, Institute of Electrical and Electronics Engineers, Aug 2011.
The definitive version is available at https://doi.org/10.1109/ISCAS.2011.5937658
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-142449473-6
International Standard Serial Number (ISSN)
0271-4310
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2025 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
02 Aug 2011
