Abstract
Significant noise will occur when the load currents of a chip contain frequency components that are close to its resonance frequency, which is mainly decided by power delivery network (PDN) capacitance and package inductance. Yet with technology scaling, the wire parasitic capacitance, which suffers from large process variations, starts to become a dominant contributor in the PDN capacitance, leading to a large resonance frequency variation across dies. It is thus important to know the resonance frequency of individual chips to effectively avoid resonance noise at runtime. Existing methods are mostly based on frequency sweeping, which are too expensive to apply to individual chips. In this paper, we propose a novel framework to predict the resonance frequency using existing on-chip noise sensors, based on the theory of 1-bit compressed sensing. Experimental results on industrial designs show that compared with frequency sweeping, our proposed framework can achieve up to 7.6x measurement time reduction under the same accuracy, with 15% resonance frequency variation. To the best of the authors knowledge, this is the very first work to point out the need of as well as a practical solution to the resonance frequency prediction for individual chips.
Recommended Citation
T. Wang et al., "1-bit Compressed Sensing based Framework for Built-in Resonance Frequency Prediction using On-chip Noise Sensors," 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, pp. 721 - 728, article no. 7372641, Institute of Electrical and Electronics Engineers, Jan 2016.
The definitive version is available at https://doi.org/10.1109/ICCAD.2015.7372641
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-146738388-2
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
05 Jan 2016
