Abstract
Retention registers have been widely used in power gated designs to store data during sleep mode. However, their excessive area and leakage power render it imperative to minimize the total retention storage size. The current industry practice replaces all registers with single bit retention ones, which significantly limits the design freedom and yields suboptimal designs. Toward this, for the first time in the literature, we propose the concept and the design of multibit retention registers, with which only selected registers need to be replaced. The technique can significantly reduce the number of bits that need to be stored and thus the leakage power but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode by 84% along with additional mode transition latency of 6 to 11 clock cycles, compared with the single bit retention register-based design. © 1982-2012 IEEE.
Recommended Citation
Y. G. Chen et al., "Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 4, pp. 507 - 518, article no. 6774551, Institute of Electrical and Electronics Engineers, Jan 2014.
The definitive version is available at https://doi.org/10.1109/TCAD.2013.2293881
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Low power; mode transition latency; multibit retention register; power gating
International Standard Serial Number (ISSN)
0278-0070
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Jan 2014
