Abstract
Through Silicon Via (TSV) is a critical enabling technique in three-dimensional integrated circuits (3D ICs). However, it may suffer from many reliability issues. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled through constrained graph decomposition. An efficient heuristic is further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 38%, compared with a seemingly more intuitive nearest-neighbor based heuristic. © 2014 EDAA.
Recommended Citation
Y. G. Chen et al., "Yield and Timing Constrained Spare TSV Assignment for Three-dimensional Integrated Circuits," Proceedings -Design, Automation and Test in Europe, DATE, article no. 6800319, Institute of Electrical and Electronics Engineers, Jan 2014.
The definitive version is available at https://doi.org/10.7873/DATE2014.118
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
3D IC; Fault-Tolerance; Reliability; TSV
International Standard Book Number (ISBN)
978-398153702-4
International Standard Serial Number (ISSN)
1530-1591
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Jan 2014
