Utilization of Buried Capacitance™: A Case Study

Abstract

Embedding capacitive layers inside the Printed Circuit Board (PCB) have demonstrated the ability to reduce the number of Surface Mount Technology (SMT) chip decoupling capacitors on the PCB surface as well as greatly improve the performance of the power distribution system. Many systems today utilize this technology, but most public information is limited to data on test vehicles or emulators. This paper utilizes simulated as well as measured product data to compare the performance of the standard design to one using various types of Buried Capacitance™ layers with a reduced number of SMT decoupling capacitors. a methodology is provided that can be utilized for other designs.

Department(s)

Electrical and Computer Engineering

International Standard Book Number (ISBN)

978-160560345-2

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 Curran Associates, Inc., All rights reserved.

Publication Date

01 Dec 2008

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