Abstract
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. the clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with minimum skew and latency. While there are a few related works in literature, none of them considers the reliability of TSVs. Accordingly, the failure of any TSV in the clock tree yields a bad chip. the naive solution using double-TSV can alleviate the problem. But the significant area overhead renders it less practical for large designs. in this paper, we propose a novel TSV fault-tolerant unit (TFU) that can provide tolerance against TSV failures in a 3D clock network. It makes use of the existing 2D redundant trees designed for pre-bond testing, and thus has minimum area overhead. Compared to the double TSV technique, the 3D clock network constructed by our TFUs can achieve 61% area reduction with 3.9% yield rate improvement on an industrial case. to the best of the authors' knowledge, this is the first practical work in literature that considers the fault tolerance of a 3D clock network. © 2011 ACM.
Recommended Citation
C. L. Lung et al., "Fault-tolerant 3D Clock Network," Proceedings - Design Automation Conference, pp. 645 - 651, article no. 5981861, Association for Computing Machinery (ACM), Jan 2011.
The definitive version is available at https://doi.org/10.1145/2024724.2024872
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
3D IC; Clock Network; Clock Tree Synthesis; Fault-tolerant; Redundant Tree; Through-Silicon Via
International Standard Book Number (ISBN)
978-145030636-2
International Standard Serial Number (ISSN)
0738-100X
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Association for Computing Machinery, All rights reserved.
Publication Date
01 Jan 2011
