Abstract
Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. through Silicon Via (TSV) formation is one of the keys enabling technologies for 3D ICs. While TSVs provide vertical connections between different dies for higher performance, they suffer from random open defects and thermo-mechanical stress. the potential yield loss can significantly increase the mass production cost, which in turn affects the profitability of 3D ICs. to address the TSV reliability issues, double TSV, shared spare TSV and TSV fault tolerant unit (TFU) techniques have been developed. in this paper, we briefly review them and use 3D clock networks as a vehicle to compare their effectiveness and overhead. ©2011 IEEE.
Recommended Citation
C. L. Lung et al., "TSV Fault-tolerant Mechanisms with Application to 3D Clock Networks," 2011 International SoC Design Conference, ISOCC 2011, pp. 127 - 130, Institute of Electrical and Electronics Engineers, Jan 2011.
The definitive version is available at https://doi.org/10.1109/isocc.2011.6138663
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
3D IC; Clock network; Clock tree synthesis; Double TSV; Fault-tolerant; Redundant tree; Shared spare TSV; Through-Silicon via
International Standard Book Number (ISBN)
978-145770710-0
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Jan 2011
