Speedup of NULL Convention Digital Circuits Using NULL Cycle Reduction

Abstract

A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, commonly referred to as the NULL cycle. The NCR technique exploits parallelism by partitioning input wavefronts, such that one circuit processes a DATA wavefront, while its duplicate processes a NULL wavefront. A NCR architecture is developed for both dual-rail and quad-rail circuits, using either full-word or bit-wise completion. To illustrate the technique, NCR is applied to case studies of a dual-rail non-pipelined 4-bit × 4-bit unsigned multiplier using full-word completion, a quad-rail non-pipelined 4-bit × 4-bit unsigned multiplier using full-word completion, and a dual-rail optimally-pipelined 4-bit × 4-bit unsigned multiplier using bit-wise completion. The application of NCR yields a speedup of 1.57, 1.55, and 1.34, respectively, over the standalone versions, while maintaining delay-insensitivity. Furthermore, NCR is applied to a single slow stage of two pipelined designs to boost the pipelines' overall throughput by 20% and 26%, respectively.

Department(s)

Electrical and Computer Engineering

Sponsor(s)

University of Missouri Research Board

Keywords and Phrases

Asynchronous Logic Design; Delay-Insensitive Circuits; Dual-Rail Encoding; Quad-Rail Encoding; Self-Timed Circuits

International Standard Serial Number (ISSN)

1383-7621

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2006 Elsevier, All rights reserved.

Publication Date

01 Jan 2006

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