Abstract
A low-complexity hardware implementation method is proposed for discrete-time frequency-selective Rayleigh fading channels. the proposed method first employs the Sum-of-Sinusoids method to generate multiple independent flat fading channel responses, then utilizes a simple weight-delay-sum filtering method to incorporate the fractionally delayed multipath rays into inter-tap correlated tap gains. It thus achieves accurate correlation properties in both inter-tap correlation and temporal correlation (or Doppler spectrum). the proposed method is implemented by an Altera Stratix II FPGA development kit and the results show excellent performance match with those by MATLAB software simulations. ©2009 IEEE.
Recommended Citation
F. Ren and Y. R. Zheng, "A Low-complexity Hardware Implementation of Discrete-time Frequency-selective Rayleigh Fading Channels," Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1759 - 1762, article no. 5118116, Institute of Electrical and Electronics Engineers, Oct 2009.
The definitive version is available at https://doi.org/10.1109/ISCAS.2009.5118116
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Discrete-time channel modeling; FPGA implementation; Frequency-selective fading channel; Sum-of-Sinusoids method
International Standard Book Number (ISBN)
978-142443828-0
International Standard Serial Number (ISSN)
0271-4310
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
26 Oct 2009
