Abstract
Hardware implementation of discrete-time triply selective Rayleigh fading channel emulators is proposed for multiple-input multiple-output (MIMO) communications. the proposed work differs from existing ones in that it incorporates temporal correlation, intertap correlation, and spatial correlation matrices into multiple uncorrelated frequency-flat fading waveforms to obtain a triply selective fading channel. the flat fading waveforms with temporal correlation or Doppler spectrum are generated using a sum-of-sinusoid method. the intertap correlation matrix associated with multipath delay spread is computed according to the channel power delay profile and transmit/receive filters. the spatial correlation matrices are predefined inputs associated with transmit and receive antenna arrangements. the square roots of the three correlation matrices are computed via singular-value decomposition and then combined in real time with the flat fading waveforms. Several fading channel examples are implemented on an Altera Stratix III EP3SL150F field-programmable gate array (FPGA) DSP development kit with fixed-point arithmetic's. a 4-by-4 MIMO triply selective channel with ten correlated delay taps per subchannel utilizes one-third of the hardware resource of the FPGA chip. the statistical properties of the emulated fading waveforms match those of the software-Based simulators and the theoretical ones. the proposed method achieves good balance between computational complexity and resource utilization. © 2010 IEEE.
Recommended Citation
F. Ren and Y. R. Zheng, "A Novel Emulator for Discrete-time MIMO Triply Selective Fading Channels," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2542 - 2551, article no. 5460922, Institute of Electrical and Electronics Engineers, Jan 2010.
The definitive version is available at https://doi.org/10.1109/TCSI.2010.2046226
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Discrete-time triply selective fading channels; field-programmable gate array (FPGA) hardware implementation; multiple-inputmultiple-output (MIMO) systems; sum-of-sinusoid (SoS) method; wireless fading channel modeling
International Standard Serial Number (ISSN)
1549-8328
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Jan 2010
Comments
National Science Foundation, Grant ECCS-0846486