Abstract
In this paper, we implement a real-time hardware triply selective Rayleigh fading simulator. This simulator incorporates the inter-tap and spatial correlation matrices into multiple uncorrelated frequency-flat Rayleigh fading waveforms (including temporal correlation) to simulate a multiple-input multiple-output (MIMO) triply selective Rayleigh fading channel. in the correlation incorporation procedure, this simulator uses a Kronecker product method to save a large amount of hardware memories. Occupying 34% hardware resources of one Stratix III FPGA chip, this simulator can simulate 4 x 4 MIMO fading channels with 10 correlated delay-taps per subchannel in real-time for a symbol rate of 3.69 μs. Accuracy of this simulator is proved by comparing the statistical properties of its outputs to corresponding theoretical values, and they match perfectly. ©2010 IEEE.
Recommended Citation
F. Ren and Y. R. Zheng, "Hardware Implementation of Triply Selective Rayleigh Fading Channel Simulators," ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, pp. 1498 - 1501, article no. 5495499, Institute of Electrical and Electronics Engineers, Jan 2010.
The definitive version is available at https://doi.org/10.1109/ICASSP.2010.5495499
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
FPGA hardware implementation; MIMO triply selective Rayleigh fading channel; Real-time simulation
International Standard Book Number (ISBN)
978-142444296-6
International Standard Serial Number (ISSN)
1520-6149
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Jan 2010
