Abstract
We propose a built-in self-test (BIST) technique for testing and diagnosis of molecular electronic based nano fabrics. the nano fabric architectures are reconfigurable in nature thus making it possible to utilize general methods similar to those employed for testing of FPGAs. However, a high defect rate in nano fabrics renders the traditional techniques ill-suited. Moreover, the nano blocks offer potential for using a partially damaged nano block due to inherent redundancy of the architecture. This paper presents the design and analysis of testing configurations and optimization scheme that minimizes testing time while improving the utilization of the nano fabric. the proposed procedure identifies the defective nano blocks in a nano fabric and generates a defect map, which can be used during design to avoid defective components in a nano fabric to increase the yield. the proposed BIST technique results in a smaller number of test configurations compared to other proposed methods and a significant reduction in the test time. This technique is suitable for architectures with a defect rate as high as 10% since all the components are tested in parallel. © 2011 IEEE.
Recommended Citation
S. Kundaikar and M. Zawodniok, "Optimized Built-in Self-test Technique for CAEN-Based Nanofabric Systems," Proceedings of the IEEE Conference on Nanotechnology, pp. 1717 - 1722, article no. 6144624, Institute of Electrical and Electronics Engineers, Dec 2011.
The definitive version is available at https://doi.org/10.1109/NANO.2011.6144624
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
BIST; CAEN; defect tolerance; nanofabric; nanowire
International Standard Book Number (ISBN)
978-145771514-3
International Standard Serial Number (ISSN)
1944-9380; 1944-9399
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Dec 2011
