Abstract
Fundamental electronic structures such as Diodes and FETs have been shown to be constructed using selectively doped semiconducting Carbon Nanotubes or Silicon Nanowires (CNTs, SiNWs) at nanometer scale. Memory and Logic cores have been proposed, that use the configurable junctions in 2-D crossbars of CNTs. These Memory and Logic arrays at this scale exhibit a significant amount of defects that account for poor a yield. Configuration of these devices in the presence of defects demands an overhead in terms of area and programming time. This work introduces a PLA configuration that makes use of fixed and adaptive redundancy in terms of the number of nanowires. This is done in order to simplify the process of programming the PLA, increase the yield, reduce the time complexity, and in turn, reduce the cost of the system. © 2007 IEEE.
Recommended Citation
M. V. Joshi and W. K. Al-Assadi, "Nanofabric PLA Architecture with Redundancy Enhancement," Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 427 - 435, article no. 4358412, Institute of Electrical and Electronics Engineers, Dec 2007.
The definitive version is available at https://doi.org/10.1109/DFT.2007.36
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-076952885-4
International Standard Serial Number (ISSN)
1550-5774
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Dec 2007
