Nanofabric PLA Architecture with Flexible Nanowire-Redundancy
Abstract
It has been shown that fundamental electronic structures such as Diodes, and FET's can be constructed using selectively doped semiconducting Carbon Nanotubes or Silicon Nanowires (CNT's, SiNWs) at nanometer scale. Memory and Logic cores using these technologies have been proposed, that use the configurable junctions in two-dimensional crossbars of CNT's. These Memories and Logic Arrays at this scale exhibit significant amount of defects that account for poor yield. Configuration of these devices in presence of defects demands for an overhead in terms of area and programming time. in this work, we introduce a PLA configuration that makes use of design-specific redundancy in terms of number of nanowires, in order to simplify the process of programming the PLA, increase the yield and reduce the time complexity and in turn, the cost of the system.
Recommended Citation
M. V. Joshi and W. K. Al-Assadi, "Nanofabric PLA Architecture with Flexible Nanowire-Redundancy," 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings, vol. 1, pp. 166 - 169, CRC Press, Aug 2007.
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-142006342-4;978-142006182-6
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 CRC Press, All rights reserved.
Publication Date
24 Aug 2007
