Evaluation of SMT Decoupling Design in a Functioning High-speed PCB
Abstract
SMT decoupling capacitor location in DC power bus design is a critical design choice. Experimental evaluation of SMT decoupling design is presented in this work for a functioning high-speed PCB transmitting 1.0625 Gb/s serial data. SMT decoupling capacitors were removed in several steps while the swept-frequency |S2J| and power bus noise were monitored. It was found that the SMT decoupling capacitors located in proximity to the test ports decreased |S21| and power bus noise at high frequencies, even far above their series resonant frequency. The hardware measurements demonstrate that local decoupling can be beneficial for high-frequency noise mitigation.
Recommended Citation
J. Fan et al., "Evaluation of SMT Decoupling Design in a Functioning High-speed PCB," IEEE International Symposium on Electromagnetic Compatibility, vol. 2, pp. 1097 - 1101, Institute of Electrical and Electronics Engineers, Dec 2001.
Department(s)
Electrical and Computer Engineering
International Standard Serial Number (ISSN)
0190-1494
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Dec 2001
