An eye diagram, a critical metric in signal integrity analysis for high-speed interconnects such as packages, interposer, and printed circuit boards (PCBs), is generated by superposition of the received waveform. Obtaining an eye diagram is time-consuming, thus signal integrity analysis is inefficient. This article reviews that have been proposed to overcome this limitation. The statistical eye diagram provides a probability distribution depending on a sampling time and voltage, therefore it can be expanded to other metrics, such as the bit-error rate and shmoo plot. This article introduces previous research on statistical eye diagrams applied to complementary metal-oxide-semiconductors (CMOSs), noise, and high-speed systems. The methods applied to CMOSs include asymmetry between the P/NMOS transistors and the nonlinearity of the CMOS. The methods applied to noise include signal and power noise. The methods applied to high-speed systems include equalizers, signaling, encoding, linear feedback shift register, and error correction code.


Electrical and Computer Engineering

Publication Status

Open Access


National Science Foundation, Grant IIP-1916535

Keywords and Phrases

Complementary metal-oxide-semiconductor (CMOS); crosstalk; double edge response (DER); encoding; equalizer; error correction code (ECC); eye diagram; multiple edge response (MER); package; pulse amplitude modulation (PAM); signal integrity (SI); single bit response (SBR); statistical eye diagram

International Standard Serial Number (ISSN)


Document Type

Article - Journal

Document Version

Final Version

File Type





© 2024 The Authors, All rights reserved.

Creative Commons Licensing

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

Publication Date

01 Jan 2024