Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
Abstract
Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits.
Recommended Citation
W. K. Al-Assadi and S. Kakarla, "Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits," Journal of Electronic Testing, Springer-Verlag, Feb 2009.
The definitive version is available at https://doi.org/10.1007/s10836-008-5083-1
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
ATPG; NULL Convention Logic (NCL); SCOAP; Design for Test (DFT); Asynchronous circuits
International Standard Serial Number (ISSN)
0923-8174
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2009 Springer-Verlag, All rights reserved.
Publication Date
01 Feb 2009
