Jitter-Aware Economic PDN Optimization with a Genetic Algorithm

Abstract

This article proposes a jitter-aware decoupling capacitors placement optimization method that uses the genetic algorithm (GA). A novel method for defining the optimization target function in regard to power delivery network (PDN) and power source-induced jitter (PSIJ) optimization based on the GA-based tool is proposed. The proposed method can provide an optimum and economic solution for the number of decoupling capacitors to use in a PDN to reach the target impedance. Then, by modifying the optimization target function with our proposed method, an optimum solution of the number of decoupling capacitors regarding the PSIJ can be obtained. The PSIJ analytical expressions are derived in conjunction with a resonant cavity model that includes the coordinates of the decoupling capacitors and the PSIJ transfer function. The GA-based optimization algorithm with the proposed target function is first applied to optimize the number of decoupling capacitors regarding the PSIJ. Finally, the measured jitters from HSPICE simulation results are used to verify our optimization method such that both the simulated results and analytically calculated results support the efficiency of our proposed optimization method.

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Comments

This work was supported in part by the National Science Foundation under Grant IIP-1916535 and in part by the French Government through the 3IA Côte d’Azur Investments in the Future Project managed by the National Research Agency (ANR) under Grant ANR-19-P3IA-0002.

Keywords and Phrases

Decoupling Capacitor; Genetic Algorithm (GA); Jitter; Power Delivery Network (PDN); Power Integrity; Power Source-Induced Jitter (PSIJ)

International Standard Serial Number (ISSN)

1557-9670; 0018-9480

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2021 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2021

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