Improving Power Supply Induced Jitter Simulation Accuracy for IBIS Model
This work presents a new algorithm for improving the simulation accuracy of power supply induced jitter (PSIJ) in input/output buffer specification (IBIS) model. The improvement is realized by modifying the switching coefficient Ku and Kd as a function of both time and power rail voltage. The incorporation of time averaged effect of the power rail noise on buffer output switching edge during the time range of buffer propagation delay is the key element for the enhanced accuracy. In addition, implementation of the proposed algorithm in an open source spice simulator Ngspice is demonstrated. The accuracy of the proposed new algorithm is validated through transistor level circuit simulations.
Y. Sun and C. Hwang, "Improving Power Supply Induced Jitter Simulation Accuracy for IBIS Model," Proceedings of the 2021 Joint IEEE International Symposium on EMC/SI/PI, and EMC Europe (2021, Raleigh, NC), pp. 1127 - 1132, Institute of Electrical and Electronics Engineers (IEEE), Aug 2021.
The definitive version is available at https://doi.org/10.1109/EMC/SI/PI/EMCEurope52599.2021.9559139
2021 IEEE International Joint Electromagnetic Compatibility Signal and Power Integrity and EMC Europe Symposium, EMC/SI/PI/EMC Europe 2021 (2021: Jul. 26-Aug. 13, Raleigh, NC)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Algorithm; Input/Output Buffer Specification (IBIS); Open Source Spice Simulator; Power Supply Induced Jitter (PSIJ); Propagation Delay
International Standard Book Number (ISBN)
Article - Conference proceedings
© 2021 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
13 Aug 2021