Improving Power Supply Induced Jitter Simulation Accuracy for IBIS Model

Abstract

This work presents a new algorithm for improving the simulation accuracy of power supply induced jitter (PSIJ) in input/output buffer specification (IBIS) model. The improvement is realized by modifying the switching coefficient Ku and Kd as a function of both time and power rail voltage. The incorporation of time averaged effect of the power rail noise on buffer output switching edge during the time range of buffer propagation delay is the key element for the enhanced accuracy. In addition, implementation of the proposed algorithm in an open source spice simulator Ngspice is demonstrated. The accuracy of the proposed new algorithm is validated through transistor level circuit simulations.

Meeting Name

2021 IEEE International Joint Electromagnetic Compatibility Signal and Power Integrity and EMC Europe Symposium, EMC/SI/PI/EMC Europe 2021 (2021: Jul. 26-Aug. 13, Raleigh, NC)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Comments

This work was supported in part by the National Science Foundation (NSF) under Grant IIP-1916535.

Keywords and Phrases

Algorithm; Input/Output Buffer Specification (IBIS); Open Source Spice Simulator; Power Supply Induced Jitter (PSIJ); Propagation Delay

International Standard Book Number (ISBN)

978-166544888-8

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2021 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

13 Aug 2021

Link to Full Text

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