Low-Power Null Convention Logic Multiplier Design based on Gate Diffusion Input Technique
The increasing power consumption in the synchronous circuits is the major concern in the semiconductor industry. The major contributor to this power consumption is the clock generator and the clock distribution. This problem can be addressed by using the asynchronous circuits. Null Convention Logic (NCL) is one of the most commonly known delay insensitive approach for designing asynchronous designs. However, realizing the NCL circuits using the commonly used complementary metal oxide semiconductor (CMOS) technique is said to increase the area and the power consumption. The low power design technique known as Gate Diffusion Input (GDI) can be used for implementing the NCL circuits to reduce both the area and the power. Application of the external input to the sources of the pMOS and nMOS transistors, allows to reduces the area and the dynamic switching. Thus, decreasing the transistor count and the power. The proposed GDI NCL technique is used for designing the 4-bit un-pipelined NCL multiplier. The design was realized and simulated in gpdk045 Cadence Virtuoso. In comparison to the CMOS model, the GDI model shows 21.6 % in transistor count and the dynamic power is reduced by 13.7 %.
P. Metku et al., "Low-Power Null Convention Logic Multiplier Design based on Gate Diffusion Input Technique," Proceedings of the 2018 International SoC Design Conference (2018, Daegu, South Korea), pp. 233-234, Institute of Electrical and Electronics Engineers (IEEE), Nov 2018.
The definitive version is available at https://doi.org/10.1109/ISOCC.2018.8649885
2018 International SoC Design Conference, ISOCC 2018 (2018: Nov. 12-15, Daegu, South Korea)
Electrical and Computer Engineering
Keywords and Phrases
Clocks; CMOS integrated circuits; Electric power supplies to apparatus; Electric power utilization; Integrated circuit design; Low power electronics; Metals; MOS devices; Oxide semiconductors; Semiconductor device manufacture; Transistors; Asynchronous circuits; Asynchronous design; Clock distribution; Complementary metal oxide semiconductors; Low power design technique; Null convention logic; Semiconductor industry; Synchronous circuits; Computer circuits
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International Standard Serial Number (ISSN)
Article - Conference proceedings
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01 Nov 2018