Low-Power Null Convention Logic Design Based on Modified Gate Diffusion Input Technique
Abstract
Null Convention Logic (NCL) is the one of the well-known clock-less approaches for designing asynchronous logic circuits. The complementary metal oxide semiconductor (CMOS) technology is usually used for implementing the NCL circuits, which as a major drawback of large area consumption and power dissipation. These limitations have been addressed by adopting a low-power design technique called Gate Diffusion Input (GDI) in this work. GDI technique allows implementing primitive logic gates using only two transistors. Thus, it not only reduces the transistor count but also the power consumption. However, GDI technique suffers a significant voltage drop across the circuit, due to its inherent voltage swings. Thus, to ensure full swing output regenerative buffers are added at the output stage which tends to increase the overall latency. In this work, a novel GDI and HYBRID (CMOS+GDI) designs are proposed to overcome the limitations of the CMOS-NCL designs. The proposed approaches were tested by realizing NCL Ripple Carry Adder (RCA). The proposed model was simulated in Cadence Virtuoso and power reduction of 14.9 % and 9.8 % has been observedfor GDI and HYBRID models, respectively.
Recommended Citation
P. Metku et al., "Low-Power Null Convention Logic Design Based on Modified Gate Diffusion Input Technique," Proceedings of the 14th International SoC Design Conference (2017, Seoul, South Korea), pp. 21 - 22, Institute of Electrical and Electronics Engineers (IEEE), May 2018.
The definitive version is available at https://doi.org/10.1109/ISOCC.2017.8368809
Meeting Name
14th International SoC Design Conference, ISOCC 2017 (2017: Nov. 5-8, Seoul, South Korea)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
CMOS Integrated Circuits; Electric Power Supplies To Apparatus; Formal Logic; Integrated Circuit Design; Logic Design; Metals; MOS Devices; Oxide Semiconductors; Transistors, Asynchronous Logic Circuits; Cadence Virtuosos; Complementary Metal-Oxide-Semiconductor Technologies; Gate Diffusion Inputs; Low Power Design Technique; Null Convention Logic; Power Reductions; Ripple Carry Adders, Computer Circuits
International Standard Book Number (ISBN)
978-153862285-8
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2018 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 May 2018
