Signal Integrity Design of Bump-Less Interconnection for High-Speed Signaling in 2.5D and 3D IC

Abstract

With the advent of 2.5D and 3D IC, micro bumps has been highlighted as the core technology for realization of 2.5D and 3D IC. However, due to the difficulties about fabrication of reliable and cost-effective micro bumps, resulting in decrease in the final chip yield. In this paper, we propose a bump-less interconnection for high-speed signaling in 2.5D and 3D IC. In the proposed interconnection, high speed signal is transmitted via coupling pads instead of micro bumps. Signal integrity of the proposed interconnection is analyzed by simulation in the frequency- and time-domain. For a more detailed analysis, the proposed interconnection and the interconnection with the micro bumps are compared. In addition, because the silicon, organic and glass interposer have been widely employed for the 2.5D and 3D IC packaging, signal integrity of the proposed interconnection on three types of the interposer is compared and analyzed.

Meeting Name

2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015 (2015: May 25-29, Taipei, Taiwan)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Busbars; Cost effectiveness; Electromagnetic compatibility; Frequency domain analysis; Integrated circuit interconnects; Three dimensional integrated circuits, Core technology; Cost effective; Frequency and time domains; High-speed signaling; High-speed signals; IC packaging; Micro-bumps; Signal Integrity, Integrated circuit design

International Standard Book Number (ISBN)

978-147996670-7

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2015

Link to Full Text

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