Modeling and Analysis of Package PDN for Computing System Based on Cavity Model

Abstract

Recent computing systems consume more than several hundred watts of power and a robust PDN design is critical to minimize power/ground (P/G) voltage fluctuation and get stable performance. In most cases, the IC package (PKG) PDN determines mid-frequency P/G noise characteristics. The PDN of our target IC package consists of more than ten thousands staggered microvias and tens of layers, representing a significant modeling challenge. Commercial tools can estimate the PKG PDN impedance via full-wave simulations, but it has several limitations at pre-layout stage. Whole simulation should be run for every small geometry changes and it takes much time. It can give circuit model seen at port, but does not provide physics-based circuit models corresponding to whole current path. In this paper we apply the cavity model, which has been previously largely used for PCB modeling, to a complex organic package structure. We here describe the assumptions used to get an equivalent circuit model for this type of geometry and the comparison of its loop inductances with commercial tools. The cavity model gives about 10 % error compared to commercial tool and the reason of error is analyzed. In addition, a study of the PKG decoupling capacitors location is performed with the goal of a minimal loop inductance. In the final paragraph, several unique features of the PKG PDN compared to PCB PDN modeling are described.

Meeting Name

IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity (2017: Aug. 7-11, Washington, DC)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Circuit Simulation; Circuit Theory; Electromagnetic Compatibility; Equivalent Circuits; Inductance; Integrated Circuits; Packaging; Anti-Pad; Cavity Model; PKG PDN; Staggered Via; Via Jogging; Void; Printed Circuit Boards; Inductance Decomposition; Package; PDN; Via Inductance

International Standard Book Number (ISBN)

978-1538622315; 978-1538622292

International Standard Serial Number (ISSN)

2158-1118

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2017 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2017

Link to Full Text

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