A Hybrid Stack-Up of Printed Circuit Board for High-Speed Networking Systems

Abstract

Printed circuit board (PCB) design is getting critical as data rate approaching 25 Gbps (Gigabit per second) and beyond in networking systems. Channel loss, noise coupling and discontinuities are limiting the performance of high-speed channels. Equalization techniques including linear, feed forward and decision feedback are widely used in high-speed SerDes channels to compensate the channel losses. But these are still not sufficient for some extra long channels, and low loss PCB dielectric materials have to be used finally. The consequence is the cost of the networking system soaring significantly. In this paper, a hybrid stack-up is proposed for PCBs used in networking systems. Electrical performance of the hybrid stack-up is investigated in both frequency-domain and time-domain, and a positive conclusion for the hybrid stack-up is reached based on its cost and electrical performances.

Meeting Name

IEEE International Symposium on Electromagnetic Compatibility (2012: Aug. 5-10, Pittsburgh, PA)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Channel Loss; Data Rates; Decision Feedback; Electrical Performance; Equalization Techniques; Feed Forward; Frequency Domains; High-Speed Channels; High-Speed Networking; Networking Systems; Noise Coupling; Printed Circuit Board Designs; Time Domain; Dielectric Materials; Electromagnetic Compatibility; Organic Pollutants; Printed Circuit Boards

International Standard Book Number (ISBN)

978-1467320610; 978-1467320603

International Standard Serial Number (ISSN)

2158-1118; 2158-110X

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2012

Link to Full Text

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