Modeling Optimization of Test Patterns used in De-Embedding Method for Through Silicon Via (TSV) Measurement in Silicon Interposer
In this paper, the electrical performance of the test patterns used in the de-embedding method for TSV characterization was studied thoroughly. For all test patterns, full wave models were built and then analyzed based on simulated electrical performances. Equivalent circuit model analysis and parametric study results of the test patterns further demonstrate the accuracy of the full wave models. Furthermore, Scanning Electron Microscopy (SEM) measurements were taken for all the test patterns, and full wave models were optimized based on the measured dimensions. Finally, the response of the TSV pair was obtained by de-embedding the pads and traces from the TSV pair simulation with the test fixtures. Good agreement between the de-embedded results with analytical characterization and the full-wave simulation for a single TSV pair was achieved.
Q. Wang et al., "Modeling Optimization of Test Patterns used in De-Embedding Method for Through Silicon Via (TSV) Measurement in Silicon Interposer," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2016, Ottawa, Canada), pp. 412-417, Institute of Electrical and Electronics Engineers (IEEE), Sep 2016.
The definitive version is available at https://doi.org/10.1109/ISEMC.2016.7571683
2016 IEEE International Symposium on Electromagnetic Compatibility, EMC 2016 (2016: Jul. 25-29, Ottawa, Canada)
Electrical and Computer Engineering
Center for High Performance Computing Research
Second Research Center/Lab
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Electric network analysis; Electromagnetic compatibility; Electronics packaging; Equivalent circuits; Integrated circuit manufacture; Optimization; Reconfigurable hardware; Scanning electron microscopy; Analytical characterization; De-embedding; Electrical performance; Equivalent circuit model; Full waves; Full-wave simulations; Silicon interposers; Through-Silicon-Via (TSV); Three dimensional integrated circuits; analytical solution; circuit analysis; SEM measurement
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International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Sep 2016