Abstract
The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.
Recommended Citation
K. Wang et al., "The PCB Level ESD Immunity Study by Using 3 Dimension ESD Scan System," Proceedings of the International Symposium on Electromagnetic Compatibility, 2004. EMC 2004, Institute of Electrical and Electronics Engineers (IEEE), Jan 2004.
The definitive version is available at https://doi.org/10.1109/ISEMC.2004.1349812
Meeting Name
International Symposium on Electromagnetic Compatibility, 2004. EMC 2004
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
ESD Scan; Fast CMOS System; Induced Loop Voltage; Susceptibility Map
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 2004
