Abstract
Electrostatic discharges (ESD) can lead to soft-errors (e.g., bit-errors, wrong resets etc.) in digital electronics. The use of lower threshold voltages and faster I/O increases the sensitivity. In the analysis of ESD problems, an exact knowledge of the affected pins and nets is essential for an optimal solution. In this paper, a three dimensional ESD scanning system which has been developed to record the ESD susceptibility map for printed circuit board is presented and the mechanisms that the ESD event couples into the digital devices is studied. The ESD susceptibility of a fast CMOS EUT is characterized by generating the susceptibility map of the EUT. A series of measurements of the noise coupled into a sensitive trace and pin during an ESD soft error event are presented.
Recommended Citation
K. Wang et al., "ESD Susceptibility Characterization of an EUT by Using 3D ESD Scanning System," Proceedings of the 2005 International Symposium on Electromagnetic Compatibility, 2005. EMC 2005, Institute of Electrical and Electronics Engineers (IEEE), Jan 2005.
The definitive version is available at https://doi.org/10.1109/ISEMC.2005.1513538
Meeting Name
2005 International Symposium on Electromagnetic Compatibility, 2005. EMC 2005
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
3D ESD Scanning System; CMOS Integrated Circuits; ESD Susceptibility Characterization; EUT; Digital Electronics; Electrostatic Discharges; Fast CMOS EUT; Integrated Circuit Testing; Noise Measurements; Printed Circuit Board; Printed Circuit Testing; Printed Circuits; Sensitivity
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2005 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 2005
