Most electrostatic discharge (ESD) generators are built in accordance with the IEC 61000-4-2 specifications. It is shown, that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprised of fast CMOS devices, while rise time and derivative of the discharge current did not correlate well. The electric parameters of typical ESD generators and ESD generators that have been modified to reflect the current and field parameters of the human metal reference event are compared and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of the first paper, of this two-paper series, are discussed with respect to reproducibility and test severity.


Electrical and Computer Engineering

Keywords and Phrases

ESD Generator; Electrostatic Discharge; Fast CMOS System; Induced Loop Voltage

Document Type

Article - Journal

Document Version

Final Version

File Type





© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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