A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are given.
S. Luan and J. Fan and W. Liu and F. Xiao and J. L. Knighten and N. W. Smith and R. Alexander and J. Nadolny and Y. Kami and J. L. Drewniak, "Extracting CAD Models for Quantifying Noise Coupling Between Vias in PCB Layouts," Proceedings of the 52nd Electronic Components and Technology Conference, 2002, Institute of Electrical and Electronics Engineers (IEEE), Jan 2002.
The definitive version is available at http://dx.doi.org/10.1109/ECTC.2002.1008118
52nd Electronic Components and Technology Conference, 2002
Electrical and Computer Engineering
Keywords and Phrases
CAD Model; CEMPIE Simulation; PCB Layout; PEEC; SPICE; Circuit Extraction; Circuit Layout CAD; Circuit Noise; Equivalent Circuits; Integral Equations; Lumped Element SPICE Model; Mixed-Potential Integral Equation; Noise Coupling; Nonparallel Traces; Parameter Extraction; Printed Circuit Layout; Via
International Standard Serial Number (ISSN)
Article - Conference proceedings
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