Tests on the Relationship between the Oxide Thickness of CMOS Chips and Their Resistance to Neutrons

Presenter Information

Justin Munson
Will Li

Abstract

The effect of neutron bombardment on the performance of selected COTS (commercial-off-the-shelf) logic chips was examined, and a test procedure was developed. Possible improvements of the test are also discussed. The chips tested were ST Microelectronics M74HC08 (oxide thickness of 550A), Fairchild Semiconductor 74AC08 (oxide thickness of250A), and Texas Instruments SN74AHC08 (oxide thickness of 185A). The chips were exposed to a neutron fluence of around 1.674E15 n/crn² and received a gamma exposure of about 5 Mrad. Slight change was seen in the operation of the TI and Fairchild chips, and significant change was seen in the ST Microelectronics chip. These changes in device operation would become a factor prirnari1y at high frequencies.

Presentation Type

Oral Presentation

Document Type

Presentation

Presentation Date

2004-2005

Recommended Citation

Munson, Justin and Li, Will, "Tests on the Relationship between the Oxide Thickness of CMOS Chips and Their Resistance to Neutrons" (2004). Opportunities for Undergraduate Research Experience Program (OURE). 249.
https://scholarsmine.mst.edu/oure/249