Abstract
Whether for military, research (space, accelerator physics) and/or civilian use, risk avoidance against radiation-induced damage is not possible with COTS parts. Thus the sensible approach is risk management. We recommend a sensible risk management approach as follows: 1) know the radiation environment of the intended application to the extent possible; 2) know the effects of ionizing radiation on the component(s) of interest; 3) know the requirements of the application; 4) identify the candidate or chosen components; 5) test the components; 6) design-in safety factor margins to the extent possible.
Recommended Citation
A. Tokuhiro and M. F. Bertino, "Radiation Resistance Testing of MOSFET and CMOS as a Means of Risk Management," IEEE Transactions on Components and Packaging Technologies, Institute of Electrical and Electronics Engineers (IEEE), Jan 2002.
The definitive version is available at https://doi.org/10.1109/TCAPT.2002.804782
Department(s)
Nuclear Engineering and Radiation Science
Second Department
Physics
Keywords and Phrases
CMOS; CMOS Integrated Circuits; MOSFET; Integrated Circuit Testing; Ionizing Radiation; Radiation Environment; Radiation Hardening (Electronics); Radiation Resistance Testing; Radiation-Induced Damage; Risk Management; Safety Factor Margins; Semiconductor Device Testing; Test
International Standard Serial Number (ISSN)
1521-3331
Document Type
Article - Journal
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2002 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 2002
