High Performance Bulk Planar 20nm CMOS Technology for Low Power Mobile Applications
Abstract
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um 2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C. © 2012 IEEE.
Recommended Citation
H. Shang and S. Jain and E. Josse and E. Alptekin and M. H. Nam and S. W. Kim and K. H. Cho and I. Kim and Y. Liu and X. Yang and X. Wu, "High Performance Bulk Planar 20nm CMOS Technology for Low Power Mobile Applications," Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers (IEEE), Jan 2012.
The definitive version is available at https://doi.org/10.1109/VLSIT.2012.6242495
Meeting Name
2012 Symposium on VLSI Technology, VLSIT 2012
Department(s)
Mechanical and Aerospace Engineering
Sponsor(s)
IEEE Electron Devices Society (EDS)
Japan Society of Applied Physics (JSAP)
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 2012
