Masters Theses
Keywords and Phrases
Crosstalk reduction; High-speed; Integrated crosstalk noise; PCB design; SerDes channel
Abstract
"With the increasing data rate of digital circuits, the differential crosstalk degrades the signal integrity performance in PCBs drastically. Usually, in the trace area, crosstalk can be isolated by stitching vias and adding shielding ground vias can also shield coupling in the ball gate array (BGA) and pin field area. The traditional way to mitigation crosstalk in the BGA and pin field area through adding more ground vias between signal pairs or increasing the spacing in between, it demonstrated us the efficiency on crosstalk cancellation efficiency but it also increases the size of products and it would be contradictory to the trend of the industry and market. The design of new channels with far less crosstalk but maintained or increased space efficiency is necessary.
The proposed pin patterns in this research mitigate the differential crosstalk dramatically, yet maintained or even increased the signal vias to ground vias ratio (S:G). S:G is the ratio of signal vias to ground pins in a specific area of PCBs, it can represent the space efficiency). Crosstalk cancellated by using the principle of symmetry on two adjacent differential signal pairs in the BGA and pin field region. Except for the pin patterns, corresponding trace routing for the advance patterns also been researched and designed to maintain the crosstalk cancellation benefits in the pin field area. After all, interconnections between the chip package and the newly designed PCB have been studied and verified regarding industry capability and reliability.
This research proposed for the SerDes channel and the validating is under the SerDes operating circumstance"--Abstract, page iii.
Advisor(s)
Fan, Jun, 1971-
Committee Member(s)
Beetner, Daryl G.
Hwang, Chulsoon
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Sponsor(s)
National Science Foundation (U.S.)
Publisher
Missouri University of Science and Technology
Publication Date
Spring 2020
Pagination
x, 55 pages
Note about bibliography
Includes bibliographic references (pages 53-54).
Rights
© 2020 Junda Wang, All rights reserved.
Document Type
Thesis - Open Access
File Type
text
Language
English
Thesis Number
T 11699
Electronic OCLC #
1164095918
Recommended Citation
Wang, Junda, "SerDes channel crosstalk mitigation methodology with industrial implementation guidance" (2020). Masters Theses. 7936.
https://scholarsmine.mst.edu/masters_theses/7936
Comments
The author appreciates the support from the National Science Foundation (NSF) under Grant IIP-1440110 for his research during his master studies.