Masters Theses
Abstract
"Static timing analysis is a key process to guarantee timing closure for modern IC designs. However, additional pessimism can significantly increase the difficulty to achieve timing closure. Common path pessimism removal (CPPR) is a prevalent step to achieve accurate timing signoff. To speed up the existing exhaustive exploration on all paths in a design, this thesis introduces a fast multi-threading timing analysis for removing common path pessimism based on block-based static timing analysis. Experimental results show that the proposed method has faster runtime in removing excess pessimism from clock paths."--Abstract, page iii.
Advisor(s)
Shi, Yiyu
Committee Member(s)
Choi, Minsu
Fan, Jun, 1971-
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Computer Engineering
Publisher
Missouri University of Science and Technology
Publication Date
Summer 2015
Pagination
vii, 25 pages
Note about bibliography
Includes bibliographical references (page 24).
Rights
© 2015 Chunyu Wang, All rights reserved.
Document Type
Thesis - Open Access
File Type
text
Language
English
Subject Headings
Timing circuits
Integrated circuits
Nanoelectromechanical systems
Thesis Number
T 10745
Electronic OCLC #
921186273
Recommended Citation
Wang, Chunyu, "Common path pessimism removal in static timing analysis" (2015). Masters Theses. 7440.
https://scholarsmine.mst.edu/masters_theses/7440