Masters Theses


Tianchen Wang

Keywords and Phrases

3D-IC; Full-chip analysis


"Through-silicon vias (TSVs) are subject to thermal fatigue due to stress over time, no matter how small the stress is. Existing works on TSV fatigue all rely on measurement-based parameters to estimate the lifetime, and cannot consider detailed thermal profiles. In this paper, we propose a new method for TSV fatigue prediction using entropy production during thermal cycles. By combining thermodynamics and mechanics laws, the fatigue process can be quantitatively evaluated with detailed thermal profiles. Experimental results show that interestingly, the landing pad possesses the most easy-to-fail region, which generates up to 50% more entropy compared with the TSV body. The impact of landing pad dimension and TSV geometries are also studied, providing guidance for reliability enhancement. Finally, full-chip fatigue analysis is performed based on stress superposition. To the best of the authors' knowledge, this is the first TSV fatigue model that is free of measurement data fitting, the first that is capable of considering detailed thermal profiles, and the first framework for efficient full-chip TSV fatigue analysis."--Abstract, page iii.


Shi, Yiyu

Committee Member(s)

Lim, Sung Kyu
Choi, Minsu


Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering


Missouri University of Science and Technology

Publication Date

Spring 2015


viii, 34 pages

Note about bibliography

Includes bibliographical references (pages 32-33).


© 2015 Tianchen Wang, All rights reserved.

Document Type

Thesis - Open Access

File Type




Subject Headings

Three-dimensional integrated circuits
Interconnects (Integrated circuit technology) -- Design and construction
Metals -- Thermal fatigue

Thesis Number

T 10746

Electronic OCLC #