Masters Theses

Luke Maresca

Abstract

"Conventional three-dimensional integrated circuits (3D ICs) stack multiple dies vertically for higher integration density, shorter wirelength, smaller footprint, faster speed and lower power consumption. Due to the large through-silicon-via (TSV) sizes, 3D design partitioning is typically done at the architecture-level With the emerging monolithic 3D technology, TSVs can be made much smaller, which enables potential block-level partitioning. However, it is still unclear how much benefit can be obtained by block-level partitioning, which is affected by the number of tiers and the sizes of TSVs. In this thesis, an 8-bit ripple carry adder was used as an example to explore the impact of TSV size and tier number on various tradeoffs between power, delay, footprint and noise. With TSMC 0.18um technology, the study indicates that when the TSV size is below 100nm, it can be beneficial to perform block-level partitioning for smaller footprint with minimum power, delay and noise overhead"--Abstract, page iii.

Advisor(s)

Shi, Yiyu

Committee Member(s)

Beetner, Daryl G.
Choi, Minsu

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Publisher

Missouri University of Science and Technology

Publication Date

2012

Pagination

vii, 45 pages

Note about bibliography

Includes bibliographical references (pages 42-44).

Rights

© 2012 Luke Maresca, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Subject Headings

Three-dimensional integrated circuitsIntegrated circuits -- Very large scale integrationIntegrated circuits -- Computer simulation

Thesis Number

T 10560

Print OCLC #

908250103

Electronic OCLC #

908261047

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