Masters Theses
Analysis and modeling of crosstalk noise and testability in Domino CMOS logic circuits
Abstract
"Domino CMOS logic offers designers the advantage of most influential circuit design parameters such as speed, higher integration density, and lower power dissipation. As a result a common practice has become to use the Domino CMOS in high performance integrated circuits. However, along with these positives comes inherently low crosstalk noise immunity. The noise immunity of Domino CMOS logic continues to reduce as the recent trends in integrated circuit technology are constantly followed...This thesis proposes analytical and statistical models for crosstalk noise in Domino CMOS logic circuits"--Abstract, page iii.
Advisor(s)
Al-Assadi, Waleed K.
Committee Member(s)
Smith, Scott C.
Choi, Minsu
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Computer Engineering
Publisher
University of Missouri--Rolla
Publication Date
Spring 2007
Pagination
ix, 89 pages
Rights
© 2007 Vipin Sharma, All rights reserved.
Document Type
Thesis - Citation
File Type
text
Language
English
Subject Headings
Crosstalk -- PreventionElectronic circuits -- NoiseMetal oxide semiconductors, Complementary
Thesis Number
T 9156
Print OCLC #
173511869
Recommended Citation
Sharma, Vipin, "Analysis and modeling of crosstalk noise and testability in Domino CMOS logic circuits" (2007). Masters Theses. 5978.
https://scholarsmine.mst.edu/masters_theses/5978
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