Masters Theses
Abstract
"This thesis describes a class of interconnection networks based on the use of a switch matrix to provide processor to memory communication. This switch allows a direct link between any processor to any memory module. The cost and performance of this network are analytically examined. The results are compared with those of a multiprocessor system using a time-shared bus configuration and it is shown that for the two extreme cases of maximum and minimum throughput, the two approaches are equivalent from a performance point of view. However, in the general case, even with a higher cost, the switch matrix provides a much better performance than the time-shared bus configuration. Furthermore, the architecture of a multiprocessor MIMD type computer using a switch matrix is investigated and Petri net techniques are used to model process coordination among processors"--Abstract, page ii.
Advisor(s)
Dawson, Darrow Finch, 1931-2007
Committee Member(s)
Tang, Min Ming
McCracken, Theodore E.
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Publisher
University of Missouri--Rolla
Publication Date
Fall 1980
Pagination
vii, 50 pages
Note about bibliography
Includes bibliographical references (pages 47-48).
Rights
© 1980 Rabah Aoufi, All rights reserved.
Document Type
Thesis - Open Access
File Type
text
Language
English
Thesis Number
T 4669
Print OCLC #
7182430
Recommended Citation
Aoufi, Rabah, "A multiprocessor system using a switch matrix configuration" (1980). Masters Theses. 5794.
https://scholarsmine.mst.edu/masters_theses/5794
