Masters Theses

Abstract

"This paper describes the known methods of generating next-state equations for asynchronous sequential circuits operating in normal fundamental mode. First, the methods that have been previously developed by other authors are explained and correlated in a simple and uniform language in order that the subtle differences of these approaches can be seen. This review is then followed by a development of a new method for generating minimal next-state equations which has some advantages over the previous methods. From the comparison of the previous known methods, it is noted that any one of these methods may be desirable for certain designs since each has some advantages that the others do not have. However, these methods also have limitations in that some methods can only be used with particular types of assignments. Also, as flow tables become larger the amount of work required to use some of these methods becomes excessive and tedious. The method developed here is a simple and straightforward approach which can be used for any unicode, single transition time assignment and will easily lend itself to computer application. The heart of this method emanates from the role that the Karnaugh map plays in the conventional approach for generating the next-state equations. The main advantage of this method seems to be its capability and proficiency in handling large flow tables"--Abstract, pages ii-iii.

Advisor(s)

Tracey, James H.

Committee Member(s)

Tranter, William H.
Engelhardt, Max

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Electrical Engineering

Publisher

University of Missouri--Rolla

Publication Date

1970

Pagination

vii, 102 pages

Note about bibliography

Includes bibliographical references (pages 88-89).

Rights

© 1970 Gregory Martin Bednar, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Subject Headings

Asynchronous circuits -- Computer-aided designAsynchronous circuits -- TestingSequential circuits -- TestingElectronic circuit design

Thesis Number

T 2513

Print OCLC #

6029633

Electronic OCLC #

871699403

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