Masters Theses

Abstract

"The challenge of extending Moore's Law past the physical limits of the present semiconductor technology calls for novel innovations. Several novel nanotechnologies are being proposed as an alternative to their CMOS counterparts, with nanowire crossbar being one of the most promising paradigms. Quite recently, a new promising clock-free architecture, called the Asynchronous Crossbar Architecture has been proposed to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing related failure modes. Even though the proposed clock-free architecture offers several merits, it is not free from the high defect rates induced due to nondeterministic nanoscale assembly. In this work, a unique Functional Test Algorithm (FTA) has been proposed and validated to test for manufacturing defects in this architecture. The proposed Functional Test Algorithm is aimed at reducing the testing overhead in terms of the time and space complexity associated with the existing sequential test scheme. In addition, it is designed to provide high fault coverage and excellent fault-tolerance via post-reconfiguration. This test scheme can be effectively used to assure true functionality of any threshold gate realized on a given PGMB. The main motivation behind this research is to propose a comprehensive test scheme which can achieve sufficiently high test coverage with acceptable test overhead. This test algorithm is a significant effort towards viable nanoscale computation"--Abstract, page iv.

Advisor(s)

Choi, Minsu

Committee Member(s)

McCracken, Theodore E.
Sedigh, Sahra

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Publisher

Missouri University of Science and Technology

Publication Date

Spring 2009

Journal article titles appearing in thesis/dissertation

  • Functional testing of asynchronous nanowire crossbar architecture
  • Post-configuration of asynchronous nanowire crossbar architecture
  • Novel functional testing technique for asynchronous nanowire crossbar system

Pagination

x, 71 pages

Rights

© 2009 Sriram Venkateswaran, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Subject Headings

Asynchronous circuits -- Design
Nanotechnology -- Testing
Nanowires

Thesis Number

T 9502

Print OCLC #

436166338

Electronic OCLC #

299090548

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